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DDR4 added several new power saving features over DDR3, including:
1. Lower power pseudo-open drain drivers for the DQ pins
2. Optional ODT Input Buffer Disable Mode For Power-Down feature
3. Optional Maximum Power Saving Mode feature
4. Optional Command Address Latency (CAL)
DDR4 is backward compatible as far back as DDR3-1333. For systems that do not need speed increases above DDR3-1333 and DDR3-1600, DDR4 can support these slower bandwidth requirements with substantially lower power requirements.
DDR4 is produced in Micron fabs around the world, including Virginia, Japan, and Taiwan.
Not really; however, DDR4 does not require an external VREFDQ, but it does provide an internally generated VREFDQ that requires calibration by the DRAM controller.
Not exactly. DDR4 still uses VTT mid-point termination on the data bus for good signal quality, however it uses pseudo open-drain drivers for less switching current compared to full push-pull drivers.
No, DDR3 requires VDD and VDDQ equal to 1.5V, VREFCA equal to 0.5 x VDD, and VREFDQ equal to 0.5 x VDDQ, while DDR4 requires VDD and VDDQ equal to 1.2V, VREFCA equal to 0.5 x VDD, and VPP equal to 2.5V.
The VPP supply replaces the internal word-line charge pumps that were present in earlier versions of DDR SDRAM including DDR3. Providing this voltage externally allows DDR4 to operate at a lower voltage level in a more cost-effective manner rather than providing the internal charge pumps.
No, the DDR4 ballout is different from the DDR3 ballout. However, DDR4 uses the same package sizes and ball pitch as DDR3.
No, DDR4 kept the 8n-bit prefetch used by DDR3; thus, BL8 is still supported.
DDR4 now has a Connectivity test mode to simplify testing with a boundary scan enabled controller. Designed to work with a boundary scan device, CT mode is supported in all Micron ×4, ×8, and ×16 devices (Though JEDEC requires only for x16). CT model allows a boundary scan device to load and read a pattern from a DDR4 in CT mode. DDR4 does not directly support IEEE 1149.1.
Yes, DDR4 supports DLL-off Mode similar to DLL Disable Mode in DDR3, up to 125 MHz
Yes, all of our 1.35V parts are backward compatible with 1.5V.
Yes. Micron supports the optional feature to disable the DLL using the Mode Register, called DLL Disable Mode. This feature allows the DRAM to operate at frequencies slower than 125 MHz, however the timing still must satisfy the refresh interval. When operating in DLL Disable Mode, special conditions apply - refer to the device data sheets for details and restrictions.
In DDR3, only one CWL is valid for a given clock frequency range. - tCKavg = 2.5ns to <3.3ns, CWL = 5 - tCKavg = 1.875ns to <2.5ns, CWL = 6 - tCKavg = 1.5ns to <1.875ns, CWL = 7 - tCKavg = 1.25ns to <1.5ns, CWL = 8
Micron supports 1Gb, 2Gb, 4Gb, and 8Gb densities.
Due to use of the 8n-prefetch architecture in DDR3, a true burst length of 4 (BL4) was not possible. Burst chop mode became available in DDR3 to help mitigate this, and is also available in newer SDRAMs. Using Burst Chop in DDR3 the last 4 bits of the burst are essentially masked. Timing in Burst Chop 4 (BC4) cannot be treated like a true BL4. For READ-to-WRITE, select WRITE-to-READ, and select WRITE-to-PRECHARGE transitions, the system can achieve clock savings in the BC4 mode. While doing READ-to-READ or WRITE-to-WRITE transitions, timing must be treated like BL8; no clock savings will be realized. DDR3 supports only either BC4 or BL8, although there is also an on-the-fly (OTF) option to switch between them via address pin A12. Refer to the device data sheets for more details.
Dynamic ODT (Rtt_WR) enables the DRAM to change termination values during a WRITE without having to perform a MODE REGISTER SET command. When Rtt_Wr and Rtt_Nom are both enabled, the DRAM will change termination values from Rtt_Nom to Rtt_Wr at the beginning of the WRITE burst. Once the burst is complete, the termination will be changed back to the Rtt_Nom value. Rtt_Wr can be used independently of Rtt_Nom, but termination will be on WRITEs only.
ZQCL stands for ZQ calibration long. This command must be issued during the power-up and initialization sequence and requires 512 clocks to complete. After power-up and initialization, the command can be issued any time the DRAM is idle. These subsequent commands only require 246 clocks. This command is used when there is more impedance error correction required than a ZQCS can provide. ZQCS stands for ZQ calibration short. This command can be performed any time the DRAM is idle. One ZQCS can correct a minimum of 0.5 percent impedance error and requires 64 clocks.
MPR is a multi-purpose register. It is a specialized register designed to allow predefined data to be read out of the DRAM. Data is one bit wide and is output on a prime DQ. For Micron DDR3 parts, the prime DQs are DQ0 for x4/x8 and DQ0/DQ8 for x16. Two locations in the MPR are defined. One allows the readout of predefined data burst—in this case, 01010101. The other location is used to output the refresh trip points from the on-die thermal sensor.
DDR3 operates at Vdd = VddQ = 1.5V ±0.075V. DDR3L operates at Vdd = VddQ = 1.35V (1.283–1.45V)
The default output driver impedance for DDR3 is 34 ohms. The impedance is based on calibration to the external 240 ohm resistor, RZQ.
RESET# is the master reset for the DRAM. It is an active LOW, asynchronous input. When the RESET# is asserted, the DRAM outputs are disabled and ODT will turn off (High-Z). The DRAM counters, registers, and data will be unknown. A RESET must be performed as part of the power-up and initialization sequence. During this sequence, the RESET# must remain LOW for a minimum of 200µs. After power-up and initialization, RESET# may be asserted at any time. Once asserted, it must stay LOW for a minimum of 100ns and a full initialization of the part must be performed afterward.
For improved signaling, DDR3 modules have adopted fly-by technology for the commands, addresses, control signals, and clocks. Due to signal routing, this technology has an inherent timing skew between the clock and DQ bus at the DRAM. Write leveling is a way for the system controller to de-skew the DQ strobe (DQS) to clock relationship at the DRAM. A simple feedback feature provided by the DRAM allows the controller to detect the amount of skew and adjust accordingly.
The ZQ calibration command can calibrate the DRAM's output drivers (Ron) and ODT values (Rtt) over process, voltage, and temperature when a dedicated 240 ohm (±1 percent) resistor is connected from the DRAM's ZQ pin to ground. In DDR3, two different calibration commands exist: ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). ZQCL is normally used during power-up initialization and reset sequences, but may be issued at any time by the controller, depending on the system environment. ZQCS is used to perform periodic calibrations to account for small voltage and temperature variations; it requires a smaller timing window to complete.
DDR3 supports RTT_nom values of 120, 60, 40, 30, and 20 ohms. Dynamic ODT values (RTT_WR) are 120 and 60 ohms.
Yes. Micron DDR3 parts will support a Tcase of 0°C to 95°C.
Using DDR2-1066 with two slots is unrealistic; simulations have not shown acceptable margins.
On-die termination (ODT) power is very application-dependent. ODT is also variable, depending on the setting in the EMR of the DRAM. Use the DDR2 power calculator to determine the values.
In a point-to-point system, ODT would only be active on WRITE cycles, and would not consume power during idle and READ cycles. On-board termination would consume power in these instances. ODT power should be about 2–3 percent of the total DDR2 DRAM power in a typical application.
The Vref pin does not draw any power, only leakage current, which is less than 5µA.
No, it must be maintained at VDDQ/2.
It’s not recommended, as the SDRAM reads will lose voltage margin; but technically, it is allowed.
Although in some cases the DRAM may work with the DLL off, this mode of operation is not documented nor supported by JEDEC. Therefore, each DRAM design may behave differently when configured to run with the DLL disabled. Micron does not support or guarantee operation with the DLL disabled. Running the DRAM with the DLL disabled may cause the device to malfunction and/or violate some DRAM output timing specifications.
The sole purpose of RDQS is to support the use of a x8-based RDIMM in a x4-based RDIMM system. The RDQS pin enables a x8 DDR2 SDRAM to emulate two x4s.
The answer depends on the design implementation. Data setup and hold timing should be designed to have 150ps or more of margin. There are Single-Ended DQS Slew Rate derating tables in the data sheet that must be used in evaluating the timing. It is recommended to fully analyze the timing in calculations, as well as using signal integrity simulations and hardware characterization.
For a READ operation, the DRAM edge-aligns the strobe(s) with the data. Most controllers sense the strobe to determine where the data window is positioned. This fine strobe/data alignment requires that each DRAM have an internal DLL. The DLL is tuned to operate for a finite frequency range, which is identified in each DRAM data sheet. Running the DRAM outside these specified limits may cause the DLL to become unpredictable. The DRAM is tested to operate within the data sheet limits. Micron does not suggest or guarantee DRAM operation outside these predefined limits.
Yes, all speed grades are backward-compatible. So, -5B can run at -6T timing and -6T voltage levels (2.5V). At DDR400 speeds, Micron parts require (in compliance with JEDEC standard) Vdd = VddQ = 2.6V ±0.1V. At slower speed grades (DDR333 through DDR200), the Micron parts are backward compatible, only requiring Vdd = VddQ = 2.5V ±0.2V.
There is no requirement to use a separate regulator to supply Vref for Micron's DDR SDRAM. However, because Vref is the reference voltage for all single-ended inputs, any noise due to sharing the regulator with other I.C.s on a board or by using a voltage divider from the VDD supply, will directly impact the noise margin on those inputs. Many multi-drop systems already have a designated voltage regulator for DDR memory. Other systems that incorporate point-to-point memory typically use a simple voltage divider resistor network between VDD and VSS. System designers should evaluate the priorities and trade-offs for each particular system and use the power supply scheme that is optimal for the system.
Micron is supporting and plans to support SDR for several years. Contact your local Micron sales representative for more information.
Micron is supporting and plans to support DDR for several years. Contact your local Micron sales representative for more information.
Yes. VREF is required during self refresh. All DDR components' on-chip address counters are still operational during self refresh mode, so VDD must be maintained within the stated data sheet limits. Again, VREF must not be disabled after the DDR memory is put into self refresh mode. Doing so could easily result in inadvertently exiting self refresh. You should understand that VREF draws almost no power; any current drawn by VREF is negligible when compared to VTT and the core VDD. DDR components typically use a differential pair common source amplifier as their SSTL_2 input receiver. Because the VREF pin is used primarily as an input to this circuit, its current draw is low. It is so low, in fact, that the device’s input leakage current (~5µA) can be considered the maximum current requirement for the VREF pin. Typical VTT power is drawn from other places on the board and depends on the other components used on the module/system in addition to DRAM devices.
The tWPST maximum specification is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
If all of the different row addresses are read or written within the refresh time (tREF), a refresh need not be performed. (The different row addresses are the same number of rows as the number of REFRESH cycles. For example, in the case of 8,192/64ms, the number of rows equal 8,192.) With DRAM, selecting row addresses causes the same action as a refresh, so a REFRESH command need not be executed.
Micron recommends that unused data pins be tied HIGH or LOW. Because Micron uses CMOS technology in DRAM manufacturing, letting them float could leave the pins susceptible to noise and create a random internal input level. Unused pins can be connected to VDD or ground through resistors.
An NC (no connect) pin indicates a device pin to which no internal connection is present or allowed. Micron recommends that no external connection be made to this pin. However, if a connection is inadvertently made, it will not affect device operation. Sometimes NC pins could be reserved for future use. Refer to the part’s data sheet to confirm whether the pin is reserved for future use. An NF (no function) pin indicates a device pin that is electrically connected to the device but for which the signal has no function in the device operation. Micron strongly recommends that no external connection be made to this pin. A DNU (do not use) pin indicates a device pin to which there may or may not be an internal connection but to which no external connections are allowed. Micron requires that no external connection be made to this pin. Refer to the part’s data sheet for more details.
Please refer to page 3 of Micron’s technical note on thermal applications: TN-00-08. If functionality or operation is not a concern, refer to storage temperature specification limits on the part’s data sheet.
JEDEC does not specify the exact state of CKE during initialization; it is supplier specific. Micron strongly recommends CKE be kept at an LVTTL logic LOW before applying a stable CLK signal. During normal operation, CKE can be tied HIGH. The initial LOW state of CKE prevents parts from receiving an illegal LMR command, which could put the part into an unknown or unexpected state.
Micron SDR SDRAM data sheets require that the clock frequency be constant during access or precharge states. However, because there is no DLL in SDRAM, it may be possible to shift the clock frequency dynamically, though this is not recommended by Micron. If a design requires shifting frequency, lowering SDRAM frequency may be OK, even if you are not doing an LMR and CAS latency change. In case of increasing frequency, ensure tCK and CAS latency specifications are met. In either case, all other data sheet timing specifications must always be adhered to.
Because SDR SDRAM does not have a DLL, there is no minimum clock frequency. However, if the device is clocked at lower frequencies, it is still important to maintain a reasonably fast slew rate on the clock edges to avoid risk of setup and/or hold-time violations. Also, for operating frequencies of 45 MHz, tCKS = 3.0ns. For more information, see LVTTL Derating for SDRAM Slew Rate Violations (TN-48-09).
Yes, the CK/CK# and DK/DK# input buffers are true differential inputs. Both sets of clocks need to meet the specifications that are defined in the Clock Input Operating Conditions tables in the RLDRAM data sheets.
Yes. However, when on-die termination (ODT) is enabled, the DNU pins will be connected to VTT. Connecting the DNU pins to GND under these circumstances will cause a substantially larger load on your VTT supply.
Simplified command set of only four commands and a Fast cycle time, as low as 7ns tRC
Multibank write is a feature that allows for SRAM-like random read access time. Using this feature can reduce RLDRAM 3’s already low tRC (<10ns) by up to 75% during reads. Through the RLDRAM 3 mode register, you can choose to write to one, two, or four banks simultaneously. By storing identical data in multiple banks, the memory controller has the flexibility to determine which bank to read the data from in order to minimize tRC delay.
Multibank write that enables SRAM-like random read capabilities. MULTIBANK REFRESH makes managing refresh overhead more flexible than ever, allowing refresh of one to four banks simultaneously. RLDRAM3 also supports a mirror function to ease layout of clamshell designs.
Yes. Even though RLDRAM 3 is a new architecture, it leverages many features from both DDR3 and RLDRAM 2 to make adoption and integration as easy as possible. The command protocol, addressing, and strobing scheme are the same as RLDRAM 2, while the I/O, AC timing, and read training register very closely resemble those found in DDR3.
Yes. Micron’s green engineering program is RoHS-compliant and conforms with most of the world’s emerging environmental standards, including those in Asia and Europe.
We design our parts to meet or exceed the JEDEC specification. As standards change, we will make the necessary changes to ensure our parts meet new specifications. Any changes made will be noted in a product change notice (PCN) and sent to our customers.
LPDDR5 achieves 6400Mbps max data rate per pin, which is 1.5x faster than LPDDR4. max data rate 4266Mbps, at the same time improving the energy efficiency (pJ/bit). Many power reduction features are introduced in LPDDR5. See the technical notes below.
TN-62-02: LPDDR5 Interface: Description of LPDDR5 Interface, how it diffres from LPDDR4X
Rev. A – 4/19
TN-62-03: LPDDR5 Training: General overview of LPDDR5 SDRAM Training
Rev. A – 5/19
TN-62-04: LPDDR5 Clocking: Description of LPDDR5 clocking, including a brief comparison with LPDDR4.
Rev. A – 5/19
TN-62-06: LPDDR5 Architecture: General overview of LPDDR5 Architecture
Rev. A – 7/19
TN-62-07: LPDDR5 ZQ Calibration: General overview of LPDDR5 ZQ calibration
Rev. A – 12/19
TN-62-08: LPDDR5 NT ODT: LPDDR5 NT ODT
Rev. A – 7/19
There is no difference in a die. We opted to add the "Mobile”, “Automotive” and “Embedded" prefix to our LPDRAM product line to align with each market segment. Mobile is for portable devices such as smartphones and tablets. Automotive is for devices relating to motor vehicles. Embedded is devices for dedicated computer system designed for one or two specific functions, unlike the general-purpose computers. In embedded applications, the device is embedded as a part of a complete device system, for example, into a digital television, a camera, and a set top box, etc. Each market segment has different product requirements such as operating temperatures which is noted in the part number. Please refer to each datasheet for the actual operating temperature range.
Operating Temperatures
Blank = Commercial temperature
IT = Industrial temperature
AT = Automotive temperature
WT = Wireless temperature
XT = Wide temperature
UT = Ultra temperature
ET = Extreme temperature
It depends. Density plays a major role in price comparisons between LPDRAM and standard SDR/DDR. Also, since LPDRAM is offered in standard configurations of x16, x32 and x64, you may be able to reduce your overall BOM cost if your application currently uses two x16 components to support a x32 bus. You could use one x32 LPDRAM instead of two x16 standard DRAM. Contact your local rep for cost information.
LPDDR3 is optimized for battery life and portability. DDR3L-RS is a low IDD6 version of the DDR3L die and offers a balance in price versus performance, along with improved standby power.
Yes. A LPDRAM part can be run at any speed equal to or slower than its rated speed grade.
Optimized for products where power consumption is a concern, our low-power LPDRAM devices combine leading-edge technologies and packaging options to meet space requirements and extend battery life. LPDRAM is available with DDR/SDR interface.
We're excited about this fast-growing market. We plan to manufacture LPDRAM for many years to come and plan to continue to shrink our designs to achieve higher densities.
We offer a comprehensive LPDRAM product portfolio, with a wide range of densities and package options (including JEDEC-standard FBGA, xMCP, and package-on-package). With Micron's extensive LPDRAM experience, our worldwide technical support team can provide the expertise and assistance you need to get your designs to market faster.
NVDIMM is a nonvolatile persistent memory solution that combines NAND flash, DRAM and an optional power source into a single memory subsystem. Micron’s NVDIMM is capable of delivering the performance levels of DRAM combined with the persistent reliability of NAND, ensuring data stored in-memory is protected against power loss.
NVDIMMs operate in the DRAM memory slots of servers to execute workloads at DRAM speeds. In the event of a power fail or system crash, an onboard controller safely transfers data stored in DRAM to the onboard nonvolatile memory, thereby preserving the data that would otherwise be lost. When the system stability is restored, the controller transfers the data from the NAND back to the DRAM, allowing the application to efficiently pick up where it left off.
Persistent memory is a new addition to the memory/storage hierarchy that enables greater flexibility in data management by providing nonvolatile, low-latency memory closer to the processor. Essentially, persistent memory accelerates application performance by removing what otherwise are constricting I/O bottlenecks placed on the application by standard storage technologies. By placing nonvolatile memory on the DRAM bus, this architecture enables customers to significantly optimize data movement in order to deliver faster access to variables stored in DRAM.
With persistent memory, system architects are no longer forced to sacrifice latency and bandwidth when accessing critical data that must be preserved. Critical data can be stored close to the processor, dramatically cutting access times. Persistent memory delivers a unique balance of latency, bandwidth, capacity and cost, delivering ultra-fast DRAM-like access to critical data and enabling system designers to better manage overall costs.
Any application where performance depends on variables stored in nonvolatile media (HDD or SSD) can benefit from NVDIMMs (most applications can be accelerated). Persistent variables include metadata logs, checkpoint state, host write caches, write buffers, journals and general logs. Applications that can be accelerated by placing these variables in NVDIMM include 2-node, high-availability storage using RAID cards, SSD mapping, RAMDisk and write caching for SSDs.
Micron will be offering three DDR4 NVDIMM products:
Legacy firmware refers to the firmware features and controller register locations for features determined by AgigA Tech, Inc., for initial DDR4 NVDIMM designs. JEDEC has now standardized the NVDIMM firmware features, register locations and APIs so that one vendor’s NVDIMM can be compatible with any other vendor’s NVDIMM. All new Micron NVDIMM solutions will leverage the JEDEC firmware interface.
Many motherboards, servers and storage appliances support NVDIMMs today. Many more will come to market in 2016. Contact your supplier for more details.
NVDIMMs leverage either block mode or direct access drivers. NVDIMMs used in conjunction with a block mode driver are compatible with OS and applications with little to no necessary software modifications. Additional performance capability can be tapped by leveraging an NVDIMM with a direct mapped driver, but OS and application software will likely need some modification. Micron is currently working with major OEMs and software companies to incorporate NVDIMM hardware, driver and software support into their mainstream products.
Embedded MultiMediaCard (e.MMC) is a NAND Flash-based memory solution defined by JEDEC that comes in a small BGA package. JEDEC defines both the hardware and software, enabling easy customer design-in and the ability to multisource.
e.MMC is a fully managed solution (all media management and ECC are handled internally), making NAND technology transitions invisible to the host and providing customers with the ability to reduce their time-to-market and to sustain products longer and more easily.
Our embedded market e.MMC products are divided into two families: automotive and broad market. This is due to the unique requirements that are required in the automotive market; thus, there is a separate product line supported by Micron’s automotive team. Broad market covers all other market segments such as consumer, gaming, server, networking, industrial, medical, military, etc. Broad market e.MMC includes two sub-families: WT with commercial temperature grade and IT with an extended temperature range.
You can order samples through the Micron Sample Center.
Yes, the JEDEC specification has to be read in conjunction with the data sheet. Micron e.MMC complies with the JEDEC standard; hence, Micron's data sheets provide information that is specific only to Micron’s e.MMC devices.
Yes, IBIS models are available for WT and IT products (JEDEC 153-/169-ball and 100-ball)
Micron is offering an extensive number of solutions for industrial customers, such as five densities and JEDEC-standard BGA 153-/169-ball and custom 100-ball packaging. All of these products will operate in the extended temperature range of -40° to 85°C.
Micron’s 100-ball e.MMC BGA package features a 1.0mm ball pitch for board routing simplification (saving PCB costs) and improved board-level reliability (temp cycling). This solution is particularly attractive to automotive, industrial, and networking market segments. See the following table for additional benefits.
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Features of 100-ball e.MMC |
Benefits |
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Large 1.0mm ball pitch |
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Large 0.45mm nominal ball diameter |
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Low ball count (compared to 153-ball e.MMC JEDEC-standard) |
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100-ball pattern contains 12 mechanical support balls (3 in each corner) |
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Flexible ball-out design |
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Micron has EOL’d its e.MMC 4.4 offering. Refer to your AE for support. A dedicated technical note “TN-FC-08: Migrating from Micron v. 4.4 e.MMC to 4.41 e.MMC” is available for review.
Yes, e.MMC provides two boot partitions to provide fast access to boot code for improved system boot time. Booting from boot partitions can provide access to stored data in ~50ms, whereas booting from the user area can take hundreds of milliseconds. However, in order to utilize the boot partitions, the chipset must be able to support booting from the boot partition. Check with your chipset vendor to understand if booting from the e.MMC boot partitions is supported.
Yes, ESG e.MMC devices support static data protection. Devices are shipped from Micron factories as COMBO with a configuration optimized for best write performance. Customers can reconfigure the devices to protect static (previously written) data if there is power loss during a write operation.
A part or all of the MLC user space can be configured as pseudo-SLC. The partition offers better reliability, endurance, and performance compared to MLC NAND.
The e.MMC specification allows customers to configure the user data area into a maximum of four separate partitions that can each be configured as MLC (default) or enhanced mode (pSLC). Enhanced mode provides better reliability in exchange for twice the space as MLC.
For more information refer to "TN-FC-40: Embedded e.MMC Configuration"
e.MMC drivers are generally available on the market due to the fact that it is an industry-standard product.
The embedded universal serial bus (eUSB) is a NAND flash-based memory solution that is compliant with the USB industry standards. USB is a widely adopted interface used across multiple platforms and operating systems, providing a low-cost, efficient data transfer solution for current applications and beyond.
eUSB is a fully managed solution that utilizes NAND memory and, through an onboard controller, internally handles all media management and ECC control. The eUSB provides customers with a complete storage solution that easily integrates into their system and, in turn, fuels a reduced time to market.
Using native SLC NAND memory, combined with a rich set of management features such as global wear leveling and dynamic data refresh, eUSB offers a superior combination of performance and reliability.
The eUSB device has a 10-pin (2x5) USB female connector compatible with the industry-standard 10-pin connector found on most motherboards. A mounting hole (connected directly to internal ground) is also provided on the PCB to ensure a stable connection to the system board. Additional holes in the PC board, utilized during manufacturing for de-paneling, can also be used as additional mounting locations if required.
Yes. Micron’s eUSB can be used as the operating system boot and main storage device. However, the application’s BIOS must support the boot mode feature, which should not be a concern for most systems that were manufactured in the last five years and support USB 2.0. In either the main storage or boot mode, the eUSB should be recognized as a fixed hard drive in the system.
Yes. Please check the part catalog for Micron’s current eUSB offerings.
Our latest generation eU500, eUSB 3.1 products do provide a method to extract relevant lifetime data through the use of SMART commands. However, previous generations of eUSB products do not support a runtime method to collect lifetime data.
Yes. Micron’s latest generation eU500 eUSB 3.1 products are backward compliant with the USB 2.0 protocol. The eU500 family also supports the same form factor, voltages and connector offerings as the previous generation e230. Please check the part catalog for Micron’s current eUSB offerings.
Planar NAND flash memory is nearing its practical scaling limits, which poses challenges for the memory industry. Industry innovation requires state-of-the-art NAND technology that scales with higher densities and lower cost per bit. 3D NAND allows flash storage solutions to continue aligning with Moore’s Law, bringing significant improvements in density while lowering the cost of NAND flash.
The 3D NAND technology developed by Intel and Micron offers significant improvements in density and cost, and it’s the first 3D NAND to use floating gate cells. This 3D NAND enables flash devices with three times higher capacity than other planar NAND die in production, and the first generation is architected to achieve better cost efficiencies than planar NAND. There are also various features that will improve latency, increase endurance and make system integration easier.
We have integrated various features to deliver improved performance and new functionality, including new programming algorithms and power management modes that help make system integration easier. See FortisFlash to learn more about these features.
The new 3D NAND technology uses floating gate cells and stacks flash cells vertically in 32 layers to achieve 256Gb multilevel cell (MLC) and 384Gb triple-level cell (TLC) die that fit within a standard package.
High-Speed NAND can read data at speeds up to 200 megabytes per second (MB/s) and can write data at speeds up to 100 MB/s. These speeds are achieved by leveraging the new ONFI 2.0 interface specification and a four-plane architecture with higher clock speeds. In comparison, conventional SLC NAND is limited to 40 MB/s for reading data and less than 20 MB/s for writing data. To maximize the performance benefits of High-Speed NAND, users must use the new ONFI 2.0 synchronous interface standard.
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
GDDR5 provides higher densities, lower external voltage and more than twice the memory bandwidth compared to its predecessor, GDDR3. GDDR5’s 4X relationship between data rate and the CK clock is unique compared to the 2X relationship in DDR3 and GDDR3.
No, GDDR5 is not a direct replacement for GDDR3 due to package size differences. GDDR3 has a 136-ball BGA package while GDDR5 has a 170-ball BGA package.
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
GDDR5X provides higher densities and lower external voltage (1.35V) compared to its predecessor, GDDR5. GDDR5X also doubles the bandwidth (10–16 Gb/s) of GDDR5 while remaining on traditional discrete package technology (FBGA).
Yes, GDDR5X has two operation modes:
Yes, GDDR5X has IEEE 1149.1 compliant boundary scan.
Micron is the first memory supplier in the industry supporting GDDR5X in mass production.
Yes, the GDDR5X SGRAM standard was first published in Dec. 2015 as JESD232. The latest JEDEC release is JESD232A.
GDDR5X is not a direct replacement for GDDR5 due to package size differences. GDDR5 has a 170-ball, 0.8mm-pitch BGA package while GDDR5X has a 190-ball, 0.65mm-pitch package.
Graphics DRAM is a category of DDR SDRAM designed to handle very large bandwidth requirements. Unlike standard DRAM, graphics DRAM is typically soldered down on the same PCB as the SoC and always supports 32 DQs per memory component. Besides graphics cards and game consoles, graphics DRAM is being used in high-bandwidth applications like networking, automotive and high-performance computing.
GDDR6 provides higher densities than previous-generation graphics memory. It doubles the bandwidth of GDDR5, extending past GDDR5X speeds. In addition, it is based on a dual-channel architecture, which enables a huge performance increase while still providing backward compatibility to GDDR5 memory access size.
No
Yes
Yes, GDDR6 has IEEE 1149.1 compliant boundary scan
Micron is leveraging its GDDR5X-based high-speed signaling know-how from more than two years of design, mass production, test and application learning in Micron GDDR6 products. This allows Micron to remain in the leading position on high-speed signaling with traditional memory components.
Yes, the GDDR6 SGRAM standard was first published in July 2017 as JESD250.
GDDR6 is not a direct replacement for GDDR5 nor GDDR5X due to package size differences. GDDR5 has a 170-ball, 0.8mm-pitch BGA package, GDDR5X has a 190-ball, 0.65-mm pitch BGA package and GDDR6 has a 180-ball, 0.75mm-pitch BGA package.
Micron reviews product roadmaps on a continuous basis to ensure that our current portfolio addresses current and future market needs. Since the early introduction of HMC, additional/alternate high-performance memories have entered the market, and the volume projects that drove initial HMC success are reaching maturity.
Micron will continue to develop and design memory for high-performance applications. GDDR has roadmap support and continues to grow in this space. Micron has also established an HBM development program.
Please work with the appropriate sales team or distribution contact to ensure last-time buy quantities are communicated to Micron prior to the last-time buy date.
See above.
Micron is the leading supplier of memory in the networking space, and we will continue to focus on and evaluate future opportunities.
The Hybrid Memory Cube Consortium (HMCC) is a working group made up of industry leaders who build, design in or enable HMC technology. The goal of the HMCC is to define industry-adoptable HMC interfaces and to facilitate the integration of HMC into a wide variety of applications that enable developers, manufacturers and enablers to leverage this revolutionary technology.
The HMCC is engaged in great exploratory work. Micron will continue to support/provide input to HMCC for technology discussions and learnings from customer engagements.
We sell SSDs (and memory) direct to the consumer through our Crucial brand. Crucial SSDs offer the same great quality, reliability, and performance of Micron SSDs, but are packaged for consumer sales. You can buy one today at crucial.com/ssd.
All of our ACS hardware comes with an installer file. Simply print out the Getting Started file and follow the directions. The C++ API source files that are included contain a PicoDrv, which represents an FPGA.
You interface like you would in any other system that utilizes PCIe® add-in cards.
Our PicoFramework provides access to all basic FPGA functionality regardless of the number of modules. The software API includes a source file called PicoDrv, which creates a PicoDrv object for each FPGA module in a system, making FPGA module communication simple.
Our PicoFramework provides access to all of the basic FPGA functionality in your system. When you build a configuration file for an FPGA, the PicoFramework software will be the top level, and your module will be instantiated inside the framework. You create a PicoDrv object for each FPGA in the system.
Programming an ACS module is accomplished via the PCIe® bus. Our EX-700 and EX-750 backplanes include a Spartan-6 FPGA that is used to load the ACS FPGA modules utilizing API calls. We also support and provide examples of DMA transfers through PCIe.
Our EX-700 and EX-750 backplanes are not technically required when using Micron’s ACS FPGA modules. Our modules can run in stand-alone with the bitfile programmed into the configuration flash, which then loads the FPGA.
No. Simply move your application’s “hot spot” to the FPGA module and then execute a function call from the main application that remains on the traditional CPU-based system.
Existing code written for serial processors should not be recompiled to run on highly parallel FPGA architectures because the many parallel benefits of the FPGA will not be realized. In fact, FPGAs are clocked much slower than CPUs (a significant power consumption benefit), so serial code would run even slower. Existing code should be analyzed to discern where the parallel nature of FPGAs offers the largest benefits, and only that part of the code should be rewritten to take advantage of the parallel nature of FPGAs. This way, the biggest benefit can be realized with the smallest effort.
The PicoFramework doesn’t constrain your selection of FPGA design tools. Use whichever tools you are currently using for your FPGA development and whichever tools you are most comfortable with.
Yes. Both Intel’s OpenCL™ and Xilinx’s SDAccel can be used with PicoFramework. Use whichever tools you are currently using for your FPGA development and whichever tools you are most comfortable with.
No. To start your own project, simply find the sample that best matches your communication model and ACS module/board, and copy it to your work directory. The copy function will provide all source files for the PicoFramework; you will just need to add your own code.
We currently support both the Xilinx® ISim and the Altera® ModelSim (Mentor’s simulator) simulators.
Micron’s Hybrid Memory Cube (HMC) controller implements the Hybrid Memory Cube Consortium’s Specification 1.1. This specification corresponds to second-generation HMC.
The HMC controller supports Intel® (formerly Altera®) Stratix® V and Arria® 10 FPGAs as well as Xilinx® Kintex® UltraScale™ and Virtex® UltraScale+™ devices.
The HMC controller’ has an interface with five 128-bit ports or a 512-bit AXI-4 interface with one 128-bit port used for host accesses.
|
Controller |
Links |
Clock Speed |
|
x8 |
15 Gb/s |
187.5 MHz |
|
x16 |
15 Gb/s |
375 MHz |
|
x8 |
12.5 Gb/s |
156.25 MHz |
|
x16 |
12.5 Gb/s |
312.5 MHz |
|
x8 |
10 Gb/s |
125 MHz |
|
x16 |
10 Gb/s |
250 MHz |
The total combined latency for the HMC controller can range from 100ns to 700ns for both the RX and TX sides in a round-trip transaction. The amount of latency depends on how the controller is configured and the features that are used. For example, if using the multiport interface, the controller creates well-formed packets according to the HMC protocol, reducing latency. The 512-bit AXI interface has read data reordering built in so read data is always returned to the user in the order requested, resulting in some packets having more latency.
The link retry feature can also contribute to the controller’s latency, bringing it up to ~300ns. This feature requires the controller to perform a complete cyclic redundancy check (CRC) on all incoming data before it is delivered. Without performing this feature, the controller latency will be at ~140ns to as low as ~100ns. Here are a few reasons to turn off the CRC checks on incoming data prior to delivery:
NOTE: In the rare event of a retry, a long tail is added to the 300ns latency.
The transceivers for Xilinx and Altera use slightly different gear boxes when they ingest 16 streams of data, turn them into 640 bits, and balance this with clock speed. Narrow is better, so 512 bits is an ideal number because it is a binary multiple, but in this case, the controller would have to process at almost 450 MHz, which runs the clock rate too fast. 650 bits, on the other hand, is as narrow as possible without running the clock rate too fast. 1024 bits, which OpenSilicon ran for a while, is too wide and too slow, causing more problems than it solves. Also, 512 bits sounds ideal, but it doesn’t work with the packet sizes. For example, the biggest packet, which is 128 bytes would be 8 flits, plus the header and tail, which is 9 flits, which does not divide into 512 bits cleanly.
The HMC itself may reschedule; it has enough performance to multitask, so it can let requests pass each other. This means that requests could return to the controller out of order. Micron can configure logic to the controller to reorder the data if your application requires it, taking into consideration your requirements for low latency versus in-order transactions.
The controller uses approximately 32,000 ALMs/LUTs and 3Mb of memory in Altera® and Xilinx® FPGAs.
GUPs have been implemented on all HMC modules, included with your purchase of the board. Also, an AXI HMC memory test sample application is provided that utilizes the 512-bit AXI interface.
The HMC controller is a fully pipelined block designed to maximize throughput. While both read and write operations require multiple clock cycles to complete, the controller allows users to issue several read and/or write requests before the first response is returned by the HMC. This pipelining of read and write requests greatly improves the throughput of the memory for user applications.
Cyclic redundancy check (CRC) error detection is used on the serializer/deserializer (SerDes) links. The CRC is generated on TX packets and checked on RX packets in the HMC controller. An error will trigger a retry on the failed packet. The HMC memory itself uses error correction code (ECC) error detection and correction inside the memory arrays themselves.
You can continue to reach your contact at the same phone number and office location. Your contact should provide you with their new Micron email address to use moving forward.
Effective Feb. 28, 2014, Elpida changed its name to Micron Memory Japan and Elpida Akita changed its name to Micron Akita, Inc.
As we continue to integrate Elpida into Micron some of the sales office locations will change. Please contact your local sales representative for further details.
Your sales representative is available to answer any questions you may have and will work closely with you to ensure that all issues are defined and resolved to the greatest degree possible.
Go to www.micron.com/careers to apply for a job.
Continue working with the same sales and customer service representatives as before. If changes are made to these contacts you will be notified immediately.
Elpida product-related information has been integrated into www.micron.com. Use these helpful hints for identifying Elpida parts and navigating our expanded part catalogs:
The ordering part number will change to include the Package Media designator (Tape & Reel or Tray). A Product Change Notification was issued in December 2013. Please contact your sales representative if you have any additional questions.
For Elpida part information, including access to Elpida-specific part catalogs and data sheets, visit micron.com/elpidaparts.
At this time, there are no plans to change the logo or part mark on Elpida branded products. If there are any changes, Micron will work to minimize any impact to our customers and will use appropriate channels to communicate those changes to our customers.
Continue any qualifications that are in progress, unless you hear otherwise from your account support team. If you have questions about support or what to qualify, please rely on your existing Micron or Elpida technical contacts for information.
Micron has made changes to the Micron Distribution network. For a complete list of authorized Micron distributors, reference the Micron Authorized Distributor list. Micron Authorized distributors will sell both Micron and Elpida products. If you have any questions or issues ordering products, please send an email to distribution@micron.com; and we will ensure that someone assists you. If over time, Micron decides to make further changes to its distribution network, we will work proactively with distribution and customers on their supply chain needs.
Micron’s terms and condition will be applicable to all purchases. Generally these are contained in a Purchase Order. For Micron Memory Japan, they are typically contained in a Master Purchase Agreement. However, if you have an existing signed agreement with Elpida, in general, the terms and conditions contained therein will continue to apply until such agreement is modified or its term ends.
Micron’s Pb-free component, die, and wafer-level products do not contain any of the six substances restricted by the China RoHS. Micron’s modules may contain Pb in both not exempted and exempted EU RoHS applications (where not reliable Pb-free alternatives are available in the market).
Micron’s products are not sold directly to consumers. The EPUP and other marking and labeling requirements apply only to the products sold directly on the consumer market. For more information contact your sales/marketing representative.
These substances are not intentionally added by Micron during the manufacturing process but can be present in trace amounts in the raw materials used to manufacture the finished products.