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    LPDDR modules

    SOCAMM2

    Micron SOCAMM2 is the first to market with a data center class modular form factor for LPDDR5X and is designed to be the flagship memory solution for AI data centers. Low-power DRAM, paired with Compression Attached Memory Module (CAMM), offers superior performance and power efficiency in a revolutionary new form factor, saving space over traditional DDR5 RDIMM configurations. ​

    World's First High-Capacity 256GB LPDRAM SOCAMM2 for Data Center Infrastructure

    The 256GB SOCAMM2 delivers 33% more capacity in the same compact footprint as its predecessor and leverages Micron’s advanced 1γ (1-gamma) DRAM process to achieve breakthrough performance and greater power efficiency.

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    Micron SOCAMM2

    World’s first 256GB SOCAMM2​

    Enabled by Micron’s breakthrough monolithic 32Gb LPDDR5X, Micron SOCAMM2 expands low‑power AI memory capabilities in the data center.

    Building on its first-to-market LPDDR module leadership, Micron introduced the 256GB SOCAMM2—delivering twice the capacity in the same compact form factor.

    2x more capacity

    Micron SOCAMM2 helps deliver faster time to first token for inference by intelligently offloading KV-cache from HBM to high-capacity LPDDR. 

    2.3x faster time to first token

    SOCAMM2 uses 32Gb die based on 1γ (1-gamma) process technology, which reduces energy per bit while scaling capacity, significantly lowering watts per gigabyte (GB).

    50% less​ power consumption

    Featured resources

    Technology Enablement Program for LPDDR5X SOCAMM2

    The Technical Enablement Program for LPDRAM SOCAMM2 offers a path into Micron for early access to technical information and support, electrical and thermal models, and information to aid in the design, development and introduction of next-generation computing platforms.

    TEP program details
    A set of multicolor digital lines aligning upward

    1 Results are based on Micron internal testing of real-time inference with Llama3 70B model (with FP16 quantization) using 500K context length and 16 concurrent users. The projected TTFT latency improvement is based on a latency of 0.12s for 2TB LPDRAM per CPU vs. 0.28s for 1.5TB LPDRAM per CPU.

    2 Results are based on Micron internal LPDDR5x power calculator, assuming estimated AI use case and conditions. ​

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