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Financial services firms face an unrelenting challenge: calculating more risk details faster using less electrical power and less rack space. From front-office derivatives pricing to end-of-day value-at-risk runs, the math never stops, and neither does the pressure to do it more efficiently.
As these workloads scale, the constraint shifts from compute to data movement. Monte Carlo simulations continuously move large datasets, making memory bandwidth a critical driver of throughput and latency.
A new STAC-A2™ audited benchmark result demonstrates what happens when memory bandwidth and processor innovation converge. The HPE ProLiant XD230 1U server (hpe.com), powered by Intel® Xeon® 6980P processors (intel.com) and equipped with Micron® 8800 MT/s DDR5 MRDIMMs (micron.com), set a new STAC-A2 performance record in cold runs of the baseline problem size, achieving the highest performance reported in audited STAC-A2 results to date.
These results were generated using an Intel-optimized STAC-A2 implementation. STAC-A2 allows vendor-specific tuning, and all results were independently audited to ensure methodological consistency.
What is STAC-A2?
STAC-A2 is the technology benchmark standard for financial market risk analysis. Designed by quants and technologists from some of the world's largest banks, it measures how quickly and efficiently a technology stack can perform Monte Carlo estimation of option Greeks, the sensitivity calculations that underpin derivatives pricing, hedging, and regulatory capital computation.
Why STAC-A2 matters in high-bandwidth memory
These workloads are massively parallel, memory-bandwidth-intensive, and deeply embedded in the daily operations of every major trading institution. When a bank runs its end-of-day risk cycle across thousands of positions, even small improvements in throughput and latency compound into materially shorter batch windows. Every second counts.
STAC-A2 reflects real-world quantitative workloads, making it a trusted framework for apples-to-apples technology evaluation across the financial services industry.
Record-setting results
The STAC-A2 tests performed by HPE in their labs delivered the highest throughput, energy efficiency, and space efficiency of all STAC-A2 audited and tested servers. See full report results linked below.
| Benchmark | Result | What It Measures |
| Portfolio Throughput | 100.8 options/sec | Options priced per second across a portfolio |
| Energy Efficiency | 231,271 options/kWh | Options priced per kilowatt-hour consumed |
| Space Efficiency | 133.8 options/hr/in cubed | Options priced per hour per cubic inch of server |
| Baseline Greeks (cold) | 0.033 seconds | Time to compute all Greeks, baseline problem size |
| Max Assets | 160 | Max assets completed in 10 min (25K paths, 252 timesteps) |
| Max Paths | 1,000,000 | Max paths completed in 10 min (5 assets, 252 timesteps) |
Figure 1: STAC-A2 Portfolio Throughput -- Generational Comparison
(click image to enlarge)
2.38x throughput over previous generation
Compared to the prior-generation platform featuring Intel Xeon Platinum 8592+ processors, the results from the test showed that this solution delivered dramatic improvements across every key metric:
- 2.38x the portfolio throughput
- 10.42x / 1.62x faster in cold/warm runs of the baseline problem size
- 2.04x / 2.07x faster in cold/warm runs of the large problem size
- 1.58x more energy efficient
- 3.26x more space efficient
These gains suggest a generational leap that can help financial institutions consolidate compute infrastructure, reduce data center footprint, and accelerate time-to-insight.
Figure 2: Micron MRDIMM Impact -- With MRDIMM vs. Without MRDIMM (Same Xeon 6980P)
(click image to enlarge)
Micron MRDIMMs: The memory advantage behind the numbers
At the heart of this benchmark result is a memory subsystem that can keep pace with 256 high-performance cores: 24 x 64GB Micron 8800 MT/s DDR5 MRDIMMs, delivering up to 1.5TB of system memory across 12 channels per socket.
Monte Carlo risk workloads are inherently memory-bandwidth-sensitive. Path generation, correlation computation, and regression steps all move large volumes of data through the memory hierarchy at every timestep.
Micron multiplexed rank DIMMs (MRDIMMs), at up to 8800 MT/s, deliver higher bandwidth at the same capacity points compared to industry-standard RDIMMs, making them a meaningful contributor to both the throughput and latency results observed in STAC-A2 testing.
Compared to a similarly configured Xeon 6980P platform using RDIMMs, the results from the test showed that this MRDIMM-equipped solution delivered:
- 1.08x higher portfolio throughput (100.8 vs. 93.2 options/sec)
- Up to 23% faster Greeks calculations on the large problem size
- 1.29x better energy efficiency (231,271 vs. 178,172 options/kWh)
- 1.65x better space efficiency (133.8 vs. 80.7 options/hr/in cubed)
For data center architects evaluating memory technology for compute-dense financial workloads, the takeaway is clear: higher memory bandwidth translates directly into faster risk calculations and more efficient infrastructure.
Intel Xeon 6980P: 128 cores engineered for financial workloads
The Intel Xeon 6980P processor with P-cores is purpose-built for the kind of parallel, compute-intensive workloads that define financial risk analytics. Each socket delivers up to 128 cores with a massive 504MB L3 cache, and Intel Advanced Vector Extensions 512 (Intel AVX-512) accelerates the vector math that is central to Monte Carlo simulations.
Intel has been developing STAC-A2 implementations for over a decade, starting with Intel Composer XE and Intel Xeon E5-2690 processors. This latest result, using the STAC-A2 Pack for oneAPI (Rev R) with the Intel oneAPI Base Toolkit 2025.3 and HPC Toolkit 2025.3, demonstrates continuous innovation as semiconductor technology advances.
Figure 3: STAC-A2 Efficiency -- Energy and Space Comparison Across Generations
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Liquid cooling meets 1U density: Power efficiency that matters
Running dual 128-core processors at production workloads inside the HPE ProLiant XD230's 1U form factor is an engineering challenge that requires careful thermal management. In this configuration, the Intel Xeon 6980P processors were liquid cooled via a coolant distribution unit (CDU), with the CDU itself cooled through the data center's primary water loop.
This hybrid approach with liquid-cooled CPUs with air-cooled supporting components enabled the HPE ProLiant Compute XD230 to pack maximum compute density into minimal rack space while maintaining the thermal headroom needed for sustained high-performance operation.
The efficiency results speak to the value of this approach:
- 1.23x more energy efficient than the same Xeon 6980P in an air-cooled configuration (INTC250422)
- 231,271 options per kWh – The highest energy efficiency of any tested Intel Xeon 6 solution
- 133.8 options/hr/in cubed – 65.8% better space efficiency than the next-best Xeon 6980P result
For institutions that face hard power caps at their facilities or have committed to sustainability targets, this combination of liquid cooling and high-bandwidth Micron MRDIMMs translates into a tangible operational advantage: more useful computation per kilowatt consumed, within existing infrastructure constraints.
Figure 4: STAC-A2 Greeks Computation Speed -- Cold Runs Across Platforms
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Greeks computation speed
Beyond throughput and efficiency, raw computation speed determines how quickly risk teams get answers. The HPE ProLiant XD230 with Micron MRDIMMs delivered the fastest cold-run Greeks times across both baseline and large problem sizes.
What this means for financial services data centers
Banks and trading firms face real constraints when deploying infrastructure: power envelopes that can't be expanded, co-location contracts with fixed rack allocations, and regulatory timelines that demand faster risk calculation turnaround.
This STAC-A2 result suggests that the combination of Micron MRDIMM memory technology, Intel Xeon 6 processors, and the HPE ProLiant XD230 liquid-cooled 1U platform can help address all three:
Lower power per calculation: Up to 1.58x better energy efficiency over the previous generation means institutions can process significantly more risk calculations within existing power envelopes while supporting sustainability commitments.
Greater compute throughput: Up to 2.38x more throughput than the previous generation means end-of-day risk runs finish faster, freeing capacity for additional scenario analysis and stress testing.
Greater compute density: Up to 3.26x better space efficiency means firms can scale risk analytics capacity within their existing data center footprint, potentially avoiding costly facility expansions.
Whether a global bank needs to reduce firm-wide risk aggregation times, a regional institution needs to expand quantitative risk coverage without growing infrastructure, or a diversified firm needs to serve more internal consumers from a shared compute platform, this solution addresses those goals simultaneously.
A proven partnership and a continued track record
This result reflects the engineering collaboration across the ecosystem. Intel authored the STAC-A2 Pack for oneAPI (Rev R) and optimized it for the Xeon 6980P architecture. Micron supplied the 8800 MT/s DDR5 MRDIMMs that delivered the memory bandwidth required to fully utilize 256 cores. The HPE ProLiant Compute XD230 provided the liquid-cooled 1U platform. And STAC independently audited every result.
This also extends Micron’s track record of powering record-setting STAC benchmark results. In a previous STAC-A2 collaboration, Micron memory helped deliver breakthrough latency results -- 35.2 milliseconds to market insight, demonstrating how memory bandwidth directly translates into faster financial analytics. This latest STAC-A2 result builds on that foundation, now with MRDIMMs pushing the boundaries of what's achievable in throughput, energy efficiency, and compute density.
Explore the full STAC-A2 audited results at www.stacresearch.com/INTC260430.
Note: All performance results cited in this blog are based on STAC-A2 audited benchmark testing (SUT ID: INTC260430) conducted on May 5, 2026. Results may vary. See www.stacresearch.com/INTC260430 for full configuration disclosure. Micron, the Micron logo, and all other Micron trademarks are the property of Micron Technology, Inc. Intel, Xeon, and the Intel logo are trademarks of Intel Corporation. HPE and ProLiant are trademarks of Hewlett Packard Enterprise. STAC and STAC-A2 are trademarks of the Securities Technology Analysis Center, LLC.
